Saideepak Reddy Mannem
Future Silicon Shaper | RTL Design + UVM Verification | Master\'s in EE | FPGA Projects
- Role
- Rtl Design and Verification Intern at Abacus Semiconductor Corporation
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Saideepak Reddy Mannem
I’m a driven Electrical and Computer Engineer with a strong foundation in RTL design, hardware validation, and functional verification. With hands-on experience across SMPS systems, embedded modules, and ASIC design flows, I bring a unique blend of hardware and verification skills to the table. My journey has taken me through board-level validation in the rail transit and power conversion industries, where I reduced EMI failures and improved system reliability through data-driven debugging and cross-functional collaboration. At the same time, I’ve built deep technical strength in SystemVerilog, UVM, and AMBA protocols, applying these to projects involving FIR filter accelerators, floating-point pipelines, and DDR memory schedulers.
Experience
Rtl Design and Verification Intern
Abacus Semiconductor Corporation
Jun 2025 — Present · San Jose, CA, US
Education
Sri Chaitanya high school
Tenth
2015 — 2016
San Jose State University
Master's degree
2024 — 2025
Sri Indu College Of Engineering & Technology
Bachelor of Technology - BTech
2019 — 2022
Government Polytechnic Yadagirigutta
Diploma of Education
2016 — 2019
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