Sai Subramanya Varun Thogarcheti

WORK HISTORY

EDUCATION

ABOUT SAI SUBRAMANYA VARUN THOGARCHETI

Design Verification Engineer with a Masters degree in Electrical EngineeringKnowledge and Skills:• Ability to verify complex systems (ASIC, SOC) using various intuitive principles of System Verilog with strong Object Oriented Programming Concepts and Universal Verification Methodology(UVM).• Working experience of more than 3yrs in emulation.• Fluency in Object Oriented Programming with SystemVerilog.• Experienced in writing checker scripts at both simulation and emulation levels.• Experience in verification using random stimulus along with functional coverage and assertion- based verification methodologies.• Sound Computer architecture and Digital Logic fundamentals.• Strong interest and exposure to RTL Design for ASIC Synthesis.• Programming ability in Verilog, System Verilog, Python, Perl and C languages.• Strong communication skills.Technical Proficiency:• Programming Languages: C, Perl, Python, Shell scripting• HDL: Verilog, System Verilog, UVM, Assembly Language, • Protocols: PCIe, AMBA APB, AHB, AXI, UART, I2C, SPI• Tools: Synopsys VCS, Cadence RTL Compiler, Cadence Virtuoso, Xilinx ISE/Vivado, ModelSimOther Skills: Proficient in Documentation, good at Organizational skills.Contact: s•••••••@gmail.com