Sai Prakash
Physical Design Engineer
- Role
- Physical Design Engineer at Intel
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sai Prakash
Having a 3+ years of experience in ASIC Back-end design, Verification, Synthesis, LEC, Timing closure(STA)- Contributed to Multiple tape-outs from 5nm,7nm and 28nm - Experience in Timing closure for large SoC- Experienced in synthesis and PNR for multiple ASICs- Hands-on experience in with industry-standard EDA tools such as Cadence Innovus, Synopsys Dc_shell, Fusion compiler,ICC2, and Primetime- My expertise includes floor planning, power planning, clock tree synthesis, and signal integrity analysis, ensuring designs meet performance, power, and area (PPA) targets.
Experience
Physical Design Engineer
May 2024 — Present · IN
Worked on advanced 5nm technology node.Having knowledge on chetah2flow.I was assigned 3 partition, one of them was multi voltage domain partition and other two partition were of high macro count.Skills that I could learn:As it was R&D project, I was asked to decide die area & ports placement too.I worked with FEV team also for passing FormalityHaving knowledge on intel caliber.I have cleared LVS, DRC\'s.I have worked on Prime time also.
Education
Bapatla Engineering College
Bachelor of Technology - BTech
2018 — 2022
Narayana Junior College - India
Intermediate
2016 — 2018
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