Sai Nikhil

About Sai Nikhil

Good Knowledge on PCIE 3.0 and worked in Data Link Layer TX RTL implementation.2. Good Knowledge on USB 3.0 and worked on RTL Integration of Protocol, Link, PHY layer and implemented tests for control transfer and bulk transfer.3. Worked on USB 2.0 VIP, Implemented USB 2.0 registers using UVM RAL(Registers, Register block, adapter, predictor) and integrated with APB Agent, Implemented CRC5, CRC16, Control transfers logic, Reset, suspend, resume and speed negotiation in driver.4. Worked on UNIPRO protocol, Implemented Test bench for DME Module, Implemented Registers using UVM RAL (Registers, Register block, Adapter, predictor) and integrated UVM RAL with AXI4 Lite VIP.Implemented DME Modular Level Testcases and RAL Functional coverage. Verified DME module twice in modular level verification and top level verification with 100% code and functional coverage and also implemented LM SAP interface assertions. Tools : VCS, Verdi, IMC, Cadence Xcelium, Simvision, Questa Sim.Languages : C, System Verilog, UVM, and VerilogIndustrial Experience: 6.5 Years

Experience

1. Staff Engineer

   Samsung Semiconductor

   Mar 2024 — Present · Bengaluru, IN

Education

• Vardhaman College of Engineering (VCEH)

  Bachelor of Technology (BTech), electronics and communication engineering

  2015 — 2018

• VNR Vignana Jyothi Institute of Engineering and Technology (VNRVJIET)

  Bachelor's degree, Electronics and Communications Engineering

  2012 — 2015