Sai Madhav
Senior Design Engineer (ASIC) at NXP
- Role
- Senior Design Engineer at 恩智浦半导体
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sai Madhav
FPGA and RTL Design Engineer with + specializing in,/, and. Adept at building - debugging using /, and coordinating across hardware and software teams for.Currently designing an - supporting at Drut Networks, with proven success in, custom peripheral interfacing, and performance benchmarking for. Strong academic foundation with a. coupled with a robust skill set in. Passionate about pushing the boundaries of - through continuous learning and system-level problem-solving.
Experience
Senior Design Engineer
Oct 2025 — Present · Hyderabad, IN
Education
Sri Chaitanya Junior College
𝗜𝗻𝘁𝗲𝗿𝗺𝗲𝗱𝗶𝗮𝘁𝗲 (𝟭𝟮𝘁𝗵)
2017
Sri Chaitanya School, SSC Board
𝗠𝗮𝘁𝗿𝗶𝗰𝘂𝗹𝗮𝘁𝗶𝗼𝗻 (𝟭𝟬𝘁𝗵)
2015
IIT Bhubaneswar
𝗕.𝗧𝗲𝗰𝗵, 𝗘𝗹𝗲𝗰𝘁𝗿𝗶𝗰𝗮𝗹,𝗘𝗹𝗲𝗰𝘁𝗿𝗼𝗻𝗶𝗰𝘀,𝗮𝗻𝗱 𝗖𝗼𝗺𝗺𝘂𝗻𝗶𝗰𝗮𝘁𝗶𝗼𝗻 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗶𝗻𝗴
2017 — 2021
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