Sai Kumar Reddy Pulagam
Design Verification Engineer @Intel | Actively seeking FTE in Design Verification and Validation/ RTL Design | MS ECE at Portland State University
- Role
- Design Verification Engineer at Intel
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sai Kumar Reddy Pulagam
Design Verification Graduate Intern | ECE Master\'s Student | Passionate about Digital…
Experience
Design Verification Engineer
Jun 2025 — Present · Santa Clara, CA, US
Education
Gokaraju Rangaraju Institute of Engineering and Technology
Bachelor of Technology - BTech
2018 — 2022
Portland State University
Master of Science - MS
2023 — 2025
Sri Chaitanya Junior College, Hydernagar
High School
2016 — 2018
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