Sai Kumar Jyothi
Analog Design engineer at Synopsys|| Master of Technology IITH( Microelectronics & VLSI)
- Role
- Senior Analog Design Engineer at Synopsys Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sai Kumar Jyothi
I am a Master of Technology student at Indian Institute of Technology, Hyderabad, pursuing my degree in Microelectronics and VLSI. I have a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Kakatiya Institute of Technology & Science. I worked as an FPGA Design Engineer at MEDHA SERVO DRIVES PVT LTD (MSDPL), a leading manufacturer of locomotive control systems and power electronics products.At MSDPL, I am responsible for understanding the system specifications, writing RTL design, simulating the design and testing the design on the FPGA board. I have worked on various communication protocols, such as UART, SPI, I2C, CAN and Manchester encoding. I have also used Cadence Virtuoso, LTSpice, and VHDL tools to design, analyze, and verify the circuits and systems. I am passionate about learning and applying new technologies to solve real-world problems. I am motivated by the opportunity to contribute to the company\'s and industry\'s innovation and growth. I can bring diverse perspectives and experiences to the team, as I have worked on different projects and domains during my internship and training periods.
Experience
Senior Analog Design Engineer
Sep 2024 — Present · Bengaluru, IN
Education
Kakatiya Institute of Technology & Science, Yerragattu Hillocks, Bheemaram, Hasanparthy, Warangal
Bachelor of Technology
2016 — 2020
Indian Institute of Technology, Hyderabad
Master of Technology - MTech
2022 — 2024
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