Sai Kishore Siliveri
Design Verification Engineer at Cadence Design Systems
- Role
- Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sai Kishore Siliveri
Design Verification Engineer with a strong track record. Deep understanding of verification methodologies (UVM, SystemVerilog) and a comprehensive knowledge of memory protocols (MRDIMM, RDIMM, DDR4/5, HBM3/4, DFI) and bus (AXI) protocols. Proven ability to verify complex features including ECC, RS_ECC, AXI Metadata, Advanced Encryption, and CRC DQ MAP. Familiar with scripting in Perl, Python and GitHub VSCode, copilot
Experience
Principal Design Engineer
Jul 2024 — Present · Bengaluru, IN
DDR/MRDIMM/HBM development
Education
SR Engineering College
Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering
2011 — 2015
National Institute of Technology Warangal
Master of Technology (M.Tech.), VLSI System Design
2015 — 2017
Bishop beretta high school
SSC
2008 — 2009
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