Sai Kashyap Nutulapati
Design Verification Engineer at AMD
- Role
- Design Verification Engineer at AMD
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sai Kashyap Nutulapati
Experienced Design Verification Engineer with 8 years of demonstrated history of working…
Experience
Design Verification Engineer
Jan 2020 — Present · Austin, TX, US
Skills
- Cadence Virtuoso
- C
- Vlsi
- Functional Verification
- Integrated Circuit Design
- Microprocessors
- Fpga
- Asic
- Computer Architecture
- Verilog
- Pspice
- Vhdl
- Simulations
- Embedded Systems
- Ieee 1149
- Dft Architectures
- Very-Large-Scale Integration (Vlsi)
- Universal Verification Methodology (Uvm)
- Arm
- Circuit Design
- Debugging
- Modelsim
- Xilinx
- Systemverilog
- Logic Design
- Analog Circuit Design
- C++
- Rtl Design
- Ieee 1500
- Digital Signal Processing
- Cmos
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