Sai Deepika
Design Verification Trainee || VLSI Enthusiastic || Verilog | SV , SVA | C ,C++ | Digital Electronics | CMOS | FPGA | 2023 graduate||
- Role
- Design Verification Trainee at Maven Silicon
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sai Deepika
RTL Design and Verification trainee at Maven Silicon, Bengaluru/Seeking for Job/internship in RTL Design and Verification/Open to new opportunities in semiconductor industry/2023 Graduate #verificationengineer #Opentowork #mavensilicon ->> TECHNICAL SKILLS Digital Electronics Verilog System Verilog System Verilog Assertions UVM [Universal Verification - Methodology] C,C++ MS Office ->> PROJECTS * Router 1×3 project [Design and verifictn]* AN effient denosing architecture for removal of impluse noise in images * FPGA implementation ->>TOOLS Modelsim Questsim ->> Hands on experience Router 1X3 Design and verification ->>BEHAVIORAL SKILLS Adaptability Punctuality Team player
Experience
Design Verification Trainee
Dec 2023 — Present · Bengaluru, IN
Education
Jawahar Navodaya Vidyalaya (JNV)
Intermediate
Sree Dattaha Group of Institutions
Bachelor of Technology - BTech
2019 — 2023
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