Sai Asrith Tabdil
Formal Verification Engineer 2 || M.tech NIT Jalandhar 2023
- Role
- Design Engineer 2 at 铿腾设计系统公司
- Location
- Kurnool, AP, IN
- LinkedIn followers
- 500 followers
About Sai Asrith Tabdil
With an MTech in Electronics and Communication Engineering from Dr B R Ambedkar National Institute of Technology, Jalandhar, I currently contribute as a Design Engineer 2 at Cadence Design Systems. Proficient in Formal Verification, USB 3.2 protocol, and regression automation, my expertise is further supported by a certification in Jasper Formal Fundamentals. At Cadence, I work with a driven team to ensure robust verification processes, leveraging tools like Verisium Debug and Jenkins for enhanced efficiency. Focused on delivering high ROI through innovative solutions, I aim to integrate technical precision with collaborative efforts to meet organizational goals and deliver value through advanced design engineering.
Experience
Design Engineer 2
Jul 2023 — Present · Bengaluru, IN
Education
Dr B R Ambedkar National Institute of Technology, Jalandhar
Master of Technology - MTech, Electronics and Communication Engineering
SRM IST Chennai
Bachelor of Technology, Electronics and Communication Engineering
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