Sai Aasrith A
Asic Design and Verification Intern @Western Semiconductor
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WORK HISTORY
Asic Design and Verification Intern @Western Semiconductor
Tempe, AZ, US
Worked on the design and verification of an AXI-based DMA IP within a SoC environment, with a focus on correctness, robustness, and system-level integration.Contributed to extending and validating unaligned transfer support in a single-channel DMA, involving partial read/write handling, byte-level masking, and correct behavior under AXI backpressure conditions.Built and executed a UVM-based verification flow, including directed and constrained-random tests, functional assertions for protocol and data-path correctness, byte-accurate reference modeling, and scoreboard-based validation of memory contents.Verified DMA operation across SoC-level integration scenarios, ensuring correct interaction with CPU-programmed control registers, AXI interconnect, system memory, and memory-mapped peripherals (UART, SPI, I2C), while accounting for realistic traffic, contention, and backpressure.Collaborated with CPU, memory, and peripheral teams to debug integration issues, analyze waveforms, close functional coverage, and ensure the DMA behaved correctly as part of the full SoC rather than in isolation.
EDUCATION
Vellore Institute of Technology
Bachelor of Technology - BTech, Electrical and Electronics Engineering
FIITJEE
MPC, Junior High/Intermediate/Middle School Education and Teaching
University of Wisconsin-Madison
Master's degree, Electrical and computer engineering
ABOUT SAI AASRITH A
Recent Master’s graduate in Computer Engineering with a strong foundation in CPU microarchitecture, cache hierarchies, and SoC design verification.Hands-on experience in SystemVerilog and UVM-based verification of AXI-connected IPs, including DMA, interconnects, memory systems, and peripherals.Proficient in constrained-random verification, assertions (protocol and functional), scoreboards, reference modeling, and functional/code coverage closure.Solid understanding of in-order and out-of-order CPU concepts, cache behavior, memory access ordering, and SoC-level data movement.Experience working across CPU, memory, and peripheral interactions in realistic SoC integration scenarios, including backpressure and corner-case analysis.Strong background in RTL design, computer architecture, and C++ based performance modeling and analysis.Interests: CPU & Cache Architecture, SoC Design & Verification, DMA & Interconnects, Memory SystemsMethodologies & Skills: SystemVerilog, UVM, Assertions, CRV, Coverage, RTL, AXI, C++
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