Sahit Kasula
Physical Design Trainee at Maven Silicon | VLSI | STA | RTL to GDSII | PnR | TCL scripting
- Role
- Physical Design Trainee at Maven Silicon
- Location
- Hyderabad, IN
- LinkedIn followers
- 500 followers
About Sahit Kasula
Passionate about VLSI challenges, I excel in pushing the limits, fueled by curiosity, problem-solving, and a dedication to continuous learning. 🧾Strong background in- Block-level Physical design implementation - Comprehensive understanding of RTL to GDSII flow- Static Timing Analysis( STA)- Digital Electronics - CMOS logic - Verilog 🧾Skilled in utilizing industry-standard EDA tools- Synopsys Design Compiler - ICC II - Synopsys Prime Time(PT)- Fusion Compiler
Experience
Physical Design Trainee
Aug 2023 — Present · Bengaluru, IN
Education
Sreenidhi Institute of Science and Technology
Bachelor of Technology - BTech
2018 — 2022
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