Sahithi Jeedimalla
Physical Design Engineer| Electrical Engineering | VLSI | VHDL | Verilog | System Verilog | Python |Embedded C | AI
- Role
- Asic Physical Design and Verification Engineer at Rivos Inc
- Location
- Charlotte, NC, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sahithi Jeedimalla
I am a recent graduate from the University of North Carolina at Charlotte, with a strong…
Experience
Asic Physical Design and Verification Engineer
Sep 2024 — Present
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