Sagar B. Girawale

About Sagar B. Girawale

Currently serving as a DFT Engineer at Google, contributing to the development of advanced semiconductor technologies with expertise in VLSI, ASIC, and embedded systems. The focus is on designing and implementing scan and MBIST architectures, preparing simulation environments, and delivering ATE patterns to enhance chip performance and reliability. With over 9 years of experience in design-for-test (DFT) methodologies, the work emphasizes driving operational efficiency and innovation in chip design and testing processes. Proficient in leveraging tools such as Tessent Logic Vision, Synopsys VCS, and Cadence Xrun, ensuring seamless collaboration in developing cutting-edge technologies.

Experience

1. Dft Engineer

   Google

   Jun 2025 — Present · Bengaluru, IN

Education

• Maven Silicon

  Certified Advanced VLSI Design and Verification course, VLSI Design and Verification

  2017 — 2017

• NATIONAL INSTITUTE OF ELECTRONICS & INFORMATION TECHNOLOGY (NIELIT)

  M.tech (ELECTRONICS DESIGN AND TECHNOLOGY), Electronics design and technology(VLSI DESIGN)

  2014 — 2016

• Shivnagar Vidya Prasarak Mandals College of engineering Malegaon Bk.Tal. Baramati, Dist.Pune

  Bachelor’s Degree, ELECTRONICS AND TELECOMMUNICATION

  2010 — 2014

Skills

• Vlsi
• Embedded Systems
• Asic
• Vhdl
• Synopsys Tools
• Verilog
• Cadence
• Mentor Graphics
• Cadstar
• C++
• Rtl Design
• Dft Compiler
• C
• Linux
• Java
• Html
• Rtl to Gdsii Design
• Matlab
• Altium Designer
• Fpga
• Microsoft Word
• Management
• Leadership
• Team Management
• Team Leadership
• Microsoft Excel
• Teamwork
• Microsoft Office
• Universal Verification Methodology (Uvm)
• Spi
• I2c