Sagar Waghela

About Sagar Waghela

10 years of hands-on Analog/Mixed-Signal Circuit Design experience.• Ability to collaborate seamlessly with other teammates, work as an individual contributor and transfer technical knowledge to the Junior Designers.• Competency in the analysis, transistor-level design and system implementation of basic analog functions using current mirrors, amplifiers, oscillators, etc.• Good working knowledge of CMOS FinFET technology and device physics.• Adequate knowledge of layout techniques for FinFET designs.• Strong knowledge of Analog/Mixed-Signal Circuit Design using Synopsys & Cadence tools.• Basic scripting knowledge: VerilogA, Tcl, Perl, MATLAB, and Simulink.• Proven track record of signing-off the blocks within aggressive project deadlines. • Good analytical and problem-solving skills.

Experience

1. Senior Staff Analog Design Engineer

   Synopsys Inc

   Feb 2025 — Present

   Designing an Analog/Mixed-signal circuits for 32 Gbps High-Speed SerDes IPs using advanced FinFet nodes ranging from 16nm down to 3nm.

Education

• San José State University

  Master of Science (MS), Electrical Engineering

  2012 — 2014

• Rizvi College of Engineering

  Bachelor's degree, Electrical and Electronics Engineering

  2006 — 2010

Skills

• Simulink
• Ic
• Cmos
• Project Planning
• Analog
• Market Research
• Team Management
• Cadence Virtuoso
• Microsoft Office
• Engineering
• Labview
• Mixed Signal
• Verilog-a
• C
• C++
• Matlab
• Vendor Management
• Project Management
• Rf
• Verilog