Sagar Shah
Sr ASIC/SoC Verification Engineer at Google
- Role
- Senior Silicon Design Verification Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sagar Shah
12 years of experience as a Verification Engineer,• Experienced in Functional Verification of design at IP and Sub-system level.• Expert in UVM based reusable and scalable Test-bench development from scratch for IP and Sub-system.• Proficient in System Verilog coding.• Exposure on CSR DV methodology.• Basic understanding of non coherent system cache.• Basic understanding of PCIe GEN6 protocol.• Exposure of Formal Verification.
Experience
Senior Silicon Design Verification Engineer
Nov 2022 — Present · Bengaluru, IN
Education
Vishwakarma Government Engineering College,chandkheda,GTU
Bachelor of Engineering (BE), Electronics And Communication
2009 — 2013
Sardar Patel and Swami Vivekanand high school,ahmedabad
SSC (GSEB)
2006 — 2007
Sardar Patel and Swami Vivekanand high school,ahmedabad
HSC (GSEB), Science (Physics, Chemistry and Maths)
2008 — 2009
Skills
- Verilog
- Functional Verification
- Universal Verification Methodology (Uvm)
- Perl
- Systemverilog
- Sata
- I2c
- Digital Electronics
- Linux
- Uvm
- Slimbus
- C++
- Vlsi
- D-Phy
- Asic
- Upf
- C
- Programming
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