Sagar Rana
Senior Silicon Design Engineer at AMD | Ex-Intel | IIT Indore
- Role
- Senior Silicon Design Engineer at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sagar Rana
Results-driven VLSI professional with 6+ years of expertise in power estimation, validation, and optimization across high-performance CPU and GPU architectures. Skilled in RTL and gate-level power methodologies, including execution, analysis, and debug strategies to drive power convergence and cross-stage correlation. Proven track record in spearheading innovation through the development of scalable tools and automation for power efficiency enhancement. Experienced in working across RTL, physical design, and signoff domains, enabling seamless collaboration and system-wide power optimization. Committed to advancing power-aware design for next-generation GPU solutions.
Experience
Senior Silicon Design Engineer
Sep 2024 — Present · Bengaluru, IN
Graphics Power Estimation and Optimization for Radeon
Education
The Maharaja Sayajirao University of Baroda
Bachelor of Engineering - BE, Electronics Engineering
2013 — 2017
Javahar Navodaya Vidyalaya Gandhinagar
HSE (12th Std), Science
2013
Indian Institute of Technology, Indore
Master of Technology - MTech, VLSI Design and Nanoelectronics
2018 — 2020
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.