Sagar Kore

About Sagar Kore

Hi I am Sagar Kore pursued M.Tech in VLSI Design from Vellore Institute of Technology (VIT) Tamil Nadu, India.• 9+ years of experience in the areas of Analog /SERDES/Custom high-speed layout design and Physical verification.• Involved in Analog/SERDES/Custom highspeed Circuit Analysis and Full chip & IP layout design from scratch. • Also experience in Job deck viewing for TSMC & Samsung Foundry. Custom lib & pdk release using the Perforce tool.• Manage & lead the rollout of the project from initial design planning, and evaluation to delivery • Collaborate closely with circuit designers on design review & strategy implementation• Volunteer to take on new advanced technology nodes to embrace the new methodology for chip design.• Worked on Different technology nodes such as 18A(1.8nm), 3nm, 7nm, 10nm, 14nm, 16nm, 22nm, and 90nm.• Experience in Floor planning, Placement, Routing, Block/Module level integration, and all physical verification checks like DRC/Full-chip DRC, LVS, Antenna, DFM, Density, ERC, Soft-checks, NMC(Methodologies check), etc. • Experience in solving issues like Latch-up, EM- IR, Self-heating, and Density issues. Along with Critical Signal - Estimating width requirements of nets and their implementation. Shielding the nets to avoid cross-talk.• Good understanding & worked on solving Layout Dependent Effects (WPE, LOD, STI, PSE, and OSE etc.) and multi-patterning.• Primary & Secondary HBM & ESD location fixing and meeting pathfinder target for IC.• Knowledge of best layout practices for minimizing impacts of process mismatchesthrough various matching techniques like common centroid, inter-digitation, addition ofdummies for BJTs, MOS, Resistor layout. And different layout technic like half-cell/Mirror Layout to match parasitics.• Full familiarity with Cadence and Mentor Graphics layout tools.• Basic understanding of scripting in Perl/Skill to develop scripts for automation is anadvantage.

Experience

1. Lead Analog Layout Engineer

   IBM

   Aug 2023 — Present · Bengaluru, IN

Education

• Vellore Institute of Technology

  Master of Technology (M.Tech.), VLSI Design

  2012 — 2014

• T.P.C.T. College of Engineering, Osmanabad

  Bachelor of Engineering (B.E.), Electronics and Telecommunication

  2006 — 2010

Skills

• Cadence Virtuoso Xl
• Microprocessors
• Circuit Design
• Tanner Eda
• Cmos
• Research
• Public Speaking
• Agilent Ads
• Modelsim
• Embedded C
• Micro Controller 8051
• Cadence Eda
• Xilinx Ise
• Cadence
• Digital Electronics
• Cadence Virtuoso Layout Editor
• Teamwork
• Cadence Virtuoso
• Digital Circuit Design
• Photoshop
• Fpga
• Microprocessor 8085
• Verilog
• Pspice
• Cadence Spectre
• C
• Vlsi
• Matlab
• Low-Power Design
• Cadence Encounter
• Windows
• Field-Programmable Gate Arrays (Fpga)