Sagar Jariwala

About Sagar Jariwala

Electrical Engineering Graduate Student majoring in Circuits and Systems with an acute interest in gaining hands-on experience in the field of ASIC/Physical Design and Verification/Validation.Looking for a challenging opportunity where I can utilize my skills and analytical ability to benefit the organization while willing to improve myself each day and strive towards excellence in my field of interest.SUMMARY OF SKILLS Strong knowledge of programming/scripting languages like Verilog, System Verilog, C/C++, Perl, Tcl, Shell. Strong knowledge of EDA tools like Cadence (Virtuoso Layout Suite, Schematic Editor, Encounter), Synopsys (Design Compiler, IC Compiler,SiliconSmart, HSPICE, Primetime, TetraMax), ModelSim IDE, and Xilinx ISE. Comprehensive knowledge of logic optimization, library characterization, RTL synthesis, floor planning, low power design techniques, multi clock domain designs and static timing analysis. Strong problem-solving skills, ability to work independently and take ownership of technical issues, good team player and strong writing/verbal communication skills. Having proficiency in : VLSI design, SOC, Physical Design, Synopsys, Logic design, Synthesis, Validation, Integrated Circuit system, Computer architecture, Scripting,Low Area, Low Power, Place and Route (P&R), Static Timing Analysis (STA)Strong coursework and hands on experience in following:Technical: IC DesignHardware Description/Verification Languages: Verilog, System VerilogScripting Languages: Perl, Tcl, ShellProgramming Languages: C, C++Tools: Cadence (Virtuoso, Spectre, SoC Encounter), Synopsys (HSPICE, Design Compiler, SiliconSmart, HSPICE, Primetime, TetraMax), Xilinx ISE, ModelSim, MATLAB

Experience

1. Staff Low Power Design Engineer

   高通

   Nov 2024 — Present · San Diego, CA, US

Education

• Gujarat Technological University

  Bachelor of Engineering (BE), Electronics and Communication Engineering

  2011 — 2015

• The University of Texas at Dallas

  Master of Science (MS), Electrical and Electronics Engineering

  2015 — 2017

Skills

• Microprocessors
• Microsoft Word
• Design Compiler
• Linux
• Modelsim
• Tcl
• C
• Cadence Encounter
• Spice
• Powerpoint
• Cadence Virtuoso
• Digital Circuit Design
• Vhdl
• Microsoft Office
• Mplab
• C++
• Synopsys Primetime
• Perl
• Teamwork
• Siliconsmart
• Java
• Xilinx Ise
• Verilog
• Matlab
• Public Speaking
• Synopsys Icc
• Soc
• Unix
• Tetramax
• Hspice