Sagar Jagtap
Digital Asic Engineer @Presto Engineering
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WORK HISTORY
Digital Asic Engineer @Presto Engineering
DK
Design & Verification • Coding for design & verification. • Memory BIST implementation. • Define synthesis timing constraints. • Synthesis and scan insertion. • Timing closure. • Write test cases and SystemVerilog assertions. • Power estimation. • Writing design reports and verification reports.Methodology • Top-level UVM testbench architecture – deploy UVM from scratch. • Build SystemVerilog verification components (SVVC) library for standard IO interfaces. • Write constrain randomized test cases and SystemVerilog assertions. • Setup and maintain regression using Jenkins. • Cadence’s stylus design flow RTL-to-Layout (P&R).Scrum Master • Setup scrum project in the Jira. • Facilitate team to build backlog and future sprints. • Conduct daily scrum meetings, retrospectives, etc.
EDUCATION
The Faculty of Engineering at Lund University
Master of Science, System-on-Chip
Savitribai Phule Pune University
Bachelor of Engineer, Electronics & Telecommunication
KTH Royal Institute of Technology
Introduction to Sustainable Electric Power Systems
SKILLS
ABOUT SAGAR JAGTAP
Development of In-house tool for variability aware delay and power modeling2. Assessment of SpyGlass constraint tool for timing constraint quality checks3. Scripting work around tools for development of automated tool flows 4. Verilog, VHDL, HSPICE, Tcl, Perl, C5. The ARM’s AMBA interface specification AXI, AHB, APB and ATB6. Constraining PCM, I2S, SIM, DDR2 and USB external interfaces of chip 7. Modelsim, DesignCompiler, PrimeTime, PrimePower, SpyGlass, Cadence Virtuoso, Silicon EnsembleSpecialties: ASIC/FPGA Design
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