Sagar Verma

About Sagar Verma

WORK EXPERIENCE• 8+Yrs of experience in Analog and Mixed signal layout design.• Contributed to successful deliveries of USB32DP, PCIe4 and MP SERDES PHYs.• Have experience on lower technology nodes such as SS3, TSMC5, TSMC6/7, SS11/14, TSMC28 and UMC28.• Have experience on managing the same database across multiple metal stacks.• Have experience to lead the top-level analog macros along with team of engineers. • Have experience to lead the complete project through each phase of deliveries e.g. LEF/GDS/CDL release to PNR team, Final LEF/GDS/CDL release to customer along with relevant documentations etc.• Have experience to work on customer issues under tight timelines to provide patch releases.• Have exposure to actively participate in project planning meetings.• Have experience in top level floor planning, power planning and routings of critical signals such as TX/RX, clock routes etc. • Have experience in layout design of performance critical blocks such as AFE, DFE, Bandgap, voltage regulators, LC tank VCO and other lane_ana and sup_ana sub-blocks.• Have experience on physical verifications such as DRC-LVS and fixing reliability issues related to Electro-migration, IR drop, Antenna Effect, Latch-up Effect, Well proximity effect etc.• Have experience on ensuring ESD robustness of IP via PERC checks— P2P, CD, LDL and TOPO.INITIATIVES AND PROBLEM SOLVING SKILLS• Took initiative to understand and solve Dtemp issue faced across multiple lower node projects such as TSMC7 and TSMC16 and delivered technical sessions to enable peers on analyzing and solving Dtemp problem of EM-SHE.• Contributed to solve PS21 correction for tx_p/tx_m nets along with ESD robustness of IP.AWARDS AND RECOGNITIONS • Bravo for execution excellenceRecognized by management for key project and for rough patches, for timely and QA\'ed deliverables.• Power-Performance-Area Optimized C16 PHY roadmapReceived IDEATHON-2021 certification on \"Power-Performance-Area Optimized 16Gbps PHY development in 6nm/7nm process technologies\" C16 has been key impact to ENT PHY roadmap in enabling 16Gbps feature-rich-PHY in advanced technology nodes.

Experience

1. Staff Engineer Deg Layout

   Micron Technology

   Nov 2023 — Present · Hyderabad, IN

Education

• Mukherjee Memorial Sr. Sec. School

  12th Pass, Science

  2004 — 2006

• Guru Gobind Singh Indraprastha University

  Bachelor of Technology (BTech), Electronics and Communication Engineering

  2007 — 2011

Skills

• Cdesigner
• C
• Programming
• Differential Pair
• Perl
• C++
• Layout Design
• Standard Cell
• Physical Verification
• Cmos
• Timing Verification
• Very-Large-Scale Integration (Vlsi)
• Vhdl
• Microsoft Office
• Microsoft Excel
• Ability to Multi-Task Under Pressure
• Current Mirrors
• Creative Thinking
• Hspice
• Analog Layouts
• Unix
• Verilog
• Python
• Sta
• Self Learning
• Laker
• Logic Pro