Sagar Patil
Senior Asic Engineer at NVIDIA
- Role
- Senior Asic Engineer at NVIDIA
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sagar Patil
Experienced Verification Engineer with a demonstrated history of working in the Semiconductor industry. Skilled in Verilog, System Verilog, C,C++, Specman and Universal Verification Methodology (UVM). Strong quality assurance professional with a Bachelor\'s Degree focused in Electronics and Communications Engineering from National Institute of Technology Warangal.
Experience
Senior Asic Engineer
Jul 2016 — Present · Hyderabad, IN
Education
National Institute of Technology Warangal
Bachelor's Degree
2009 — 2013
Skills
- Functional Verification
- Vlsi
- Quartus
- Matlab
- Uvm
- Android Sdk
- Java
- Android Development
- C
- Programming
- Algorithms
- Linux
- C++
- Multisim
- Verilog
- Pspice
- Vhdl
- Data Structures
- Very-Large-Scale Integration (Vlsi)
- Red Hat Linux
- Simulink
- Embedded Systems
- Xilinx
- Rtl Verification
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