Sagar Jagadale

About Sagar Jagadale

Skilled Verification Engineer with 18 years of experience in complex IP/SS/SoC Verification for Semiconductor Industry. SUMMARY – Diversified experience in ASIC verification for storage, networking and power management ASICs.– Predominantly worked in CPU based System Verification (ARM A53, Tensilica-LX4, TI’s MSP430, ARM7), AMBA family [AXI/AHB/APB], OCP, I2C, Bus architectures, Memory controller, Encryption, Complex Address Translation, Networking protocols (Sonet/SDH/DSL).– PCIe SubSystem verification with complex IPs (BridgeUnit, ATS, PHY+Controller, MMU), CXL Bases SS Verification- AI/ML IPs for Media Processing [Image Processing IP, Video Decode IP, Master Control IP]– Expertise in defining Verification Strategy, Testplan & Functional Coverage Plan for IP/SS/SoC verification. – Hands-on experience in architecting & developing re-usable, coverage driven verification environments using SystemVerilog+UVM & SpecmanE+eRM. – Involved in developing and maintaining Verification Automation Infrastructures (SVN/ClearCase/DesignSync/Perl/SQL), Regression Tools like Hudson (Oracle), automated functional coverage generation script. – Experience in leading teams to ensure high quality timely deliverables. Strong adherence to process driven work culture- Experience in Leading PostSi Validation team. – Efficient team player, quick learner, detail oriented & outspoken individual.

Experience

1. Principal Engineer

   NVIDIA

   Aug 2023 — Present · Bengaluru, IN

Education

• CEDTI Aurangabad

  M.Tech, Electronics design & Technology

  2002 — 2004

• KET's V.G.Vaze College

  HSC, Science

  1995 — 1997

• Parshvanath College of Engineering Thane

  Bachelor of Engineering, Instrumentation Engineering

  1997 — 2001

Skills

• Spi
• Jtag
• Ncsim
• Asic
• Systemverilog
• Uvm
• Specman
• I2c
• Soc
• Xilinx Ise
• Functional Verification
• Perl
• Vhdl
• Verilog
• Arm
• Modelsim
• C