Sadiq Mohiuddin

About Sadiq Mohiuddin

25+ years of Chip design experience in various aspects of physical design convergence from Synthesis to Tape-In of mixed-signal high-speed & low-power ASIC\'s from 10/100/Gig & 10G PHYs, CPU Chipsets, CPU Cores to Automotive chips.* Currently working as the backend Implementation lead @ Broadcom and successfully taped out Automotive and 10G+ Physical Layer Products.* Previously @ Intel worked on Design Planning, Physical Design Implementation & Convergence Owner for 3 generations of Intel Xeon Phi CPU (ATOM) Core for the Projects: Knights Landing (14nm), Knights Corner (22nm), Knights Ferry (45nm)* The last successfully taped out project @ Intel was the Xeon Phi processor is ranked World\'s #1 in the Green500 (Low-Power) list! The 2nd generation Xeon Phi design was used to build the World’s #1 TOP500 Super Computer (MilkyWay2 System)* Expert in design implementation of challenging high speed digital blocks involving several complexities like latches, hard macros, floorplanning options, preroute planning, congestion, crosstalk, timing, low-power optimization, and negotiating critical external timing interfaces. Solving complex design problems to converge CPU design with ASIC methodology working through severe limitations of Synopsys DCT/ICC/PT tools in handling latches.

Experience

1. Senior Principal Design Engineer - Ic Design

   Broadcom

   May 2014 — Present · Irvine, CA, US

   Physical design & implementation of complex physical layer devices for 10/100/1G, 10GBase-T and automobile applications to connect everything everywhere, all-the-time!

Education

• Little Flower Junior College

  College, Mathematics, Physics & Chemistry

  1991 — 1993

• California State University-Sacramento

  Master of Business Administration (MBA)

  2006 — 2007

• Osmania University

  Bachelor of Science (B.S.), Electronics and Communication Engineering

  1993 — 1997

• Arizona State University

  Masters in Electrical Engineering, Solid State Electronics, VLSI Design

  1997 — 1998

Skills

• Dft
• Floorplanning
• Fpga
• Logic Design
• Asic
• Chipset
• Physical Design
• Synopsys Primetime
• Vhdl
• Intel
• Hardware Architecture
• Clock Tree Synthesis
• Mixed Signal
• Verilog
• Low-Power Design
• Conformal Lec
• Arm
• High-Speed Digital Design
• Processors
• Cmos
• Synopsys Icc Design Planning
• Microarchitecture
• Logic Synthesis
• Drc
• Ethernet
• Semiconductors
• Leadership
• Soc
• Embedded Systems
• Eda
• Static Timing Analysis
• Synopsys Tools
• Silicon
• Signal Integrity
• Vlsi
• Ic
• Timing Closure
• Integrity
• Formal Verification
• Physical Verification