Fnu Sachin

About Fnu Sachin

I have a master’s degree in Electrical Engineering, with experience in VLSI Design, RTL Coding, DFT and Verification. My skills were rigorously tested during my master’s and I want to prove them on the field. I want to work in a team of skilled and passionate engineers who are motivated to solve problems same as I am. A brief description of my expertise, experience and interests are as follows:• Worked on front-end development of a full-custom ASIC chip (Design specification, block-level design, logic design, RTL design, functional verification, CMOS transistor level design, floorplanning, BSD, timing closure, tape-out and post-Si validation).• Worked on back-end development of 2 chips with Synopsys tools (RTL Design, DFT Design, functional verification, static timing analysis, synthesis, floorplanning, timing closure and power analysis).• Worked on tools such as Synopsys Design Compiler, Power Compiler, IC Compiler, Primetime, ModelSim, Altera DE0-Nano-SoC, HSPICE, IRSIM and GCC.• Worked on C++, HDLs like VHDL, Verilog and SystemVerilog and scripting in PERL and TCL.• Experienced in DFT, Verification, Computer Architecture and FPGA development. I have also worked for 2 years in India as a Systems Engineer on Software Development. It helped me gain 2 very important skills, managing my time and work and working with a large team. My hard work was appreciated, and I was awarded High-Performance Incentive. After working for 2 years, I felt I want to go back to my passion of working in the semiconductor field.I am authorized to work full-time anywhere in the US and willing to relocate if required. If you feel like my skills and background matches your requirements, feel free to reach out.Sachin,s••••••••@gmail.com51••••••58

Experience

1. Product and Test Engineer

   Qualcomm Technologies International, Ltd

   Jul 2020 — Present · San Diego, CA, US

   Working as Product Development and Test Engineer, I get to be part of the entire product bring up flow, starting at DFT insertion. My most active work starts post tape out, with the beginning of pattern generation, test setup, test hardware design and silicon verification and validation upon docking. Some of processes I am involved in:Wafer sorting and test characterizxation using Advantest 93K Tester/probers.Test plan bring up and validation.Product and Package Qualifications, including HTOL, ESD, MSL etc.Pattern Debug and failure analysis.Yield analysis and production projections.Power and Performance testing to match KPIs.

Education

• Guru Gobind Singh Indraprastha University

  Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering

  2010 — 2014

• University of Cincinnati

  Master of Engineering (M.Eng.), Electrical Engineering

  2016 — 2018

• D.L.D.A.V. Model School

  S.S.C, Mathematics and Computer Science

  2008 — 2009