Sachin Jeevanagi
Senior Design Engineer
- Role
- Design Engineer at STMicroelectronics
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sachin Jeevanagi
7 years of industrial experience in DFT implementation which includes scan and compression logic insertion, ATPG Pattern generation and verification. Basic Knowledge about Boundary scan. Extensively worked with Mentor tools like Tessent shell for scan insertion and ATPG generation, And VCS, ModelSim for pattern simulation
Experience
Design Engineer
Dec 2021 — Present · Bangalore Urban, IN
Education
P D A College of Engineering, GULBARGA
Bachelor of Engineering - BE, Instrumentation Technology/Technician
2013 — 2017
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