Sabnam Parveen

About Sabnam Parveen

PDK Engineer at Intel, performing Runset QA for DRC flows on advanced nodes. I perform coverage-driven regressions, validate rule coverage, and ensure alignment with foundry specs to support robust PDK delivery.Previously, I contributed to Static Timing Analysis (STA) as a Physical Design Timing Intern at Intel, where I served as Quality Checker Tool Owner for 15+ partitions, automating checks using TCL/BASH and reducing manual effort by up to 95%.Prior to that, I worked as a Project Assistant on a SERB-DST funded research project at NIT Durgapur, developing MoS₂-based flexible gas sensors using CVD and gaining hands-on experience in nano device fabrication and 2D materials.I hold an M.Tech in Microelectronics & VLSI from NIT Durgapur, with skills in RTL to GDSII flow, Cadence tools, STA, and physical design. Proficient in Genus, Innovus, Virtuoso, Calibre, ICV, ICV, Pegasus, and scripting in TCL, BASH, Python.Feel free to connect if you\'d like to discuss VLSI, PDK development, STA, or collaborative opportunities in semiconductor design.

Experience

1. Pdk Engineer

   Intel

   Jun 2025 — Present · Bengaluru, IN

   Responsiblities:* Executing Runset QA for the DRC flow of the VIA module on Intel’s advanced process node.* Developing coverage-driven regressions from foundry SPEC to validate functional and geometric Runset intent.* Analyzing Runset-to-spec alignment and reporting DRC issues to SPEC and DEV teams.

Education

• NSHM Knowledge Campus Durgapur Group of Institutions 273

  Bachelor of Technology - BTech, Electronics and Communication Engineering

• Bidhan Chandra Institution for Girls

  Higher Secondary School Certificate (12th), Science

• National Institute of Technology Durgapur

  Master of Technology - MTech, Microelectronics and VLSI

• Benachity Netaji Vidyalaya

  Secondary School Certificate (10th)