Sabira Enayet
ATTD Yield Defect Reduction GL Wafer Level Assembly and Pkg Assembly
- Role
- Attd Yield Defect Reduction Gl at Intel
- Location
- Chandler, AZ, US
- LinkedIn followers
- 500 followers
Manufacturing & ProductionView LinkedIn profile
Experience
Attd Yield Defect Reduction Gl
Mar 2022 — Present · US
Education
Arizona State University
Master of Science - MS
Bangladesh University of Engineering and Technology
Bachelor of Science - BS
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