Sabarish Potnuru
Staff Design Verification Engineer at Microsoft | IIT Hyderabad | SV, UVM, C++, DV, IP, Perl | Ex-Marvell, NXP
- Role
- Senior Silicon Engineer at Microsoft
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sabarish Potnuru
Highly skilled and experienced Verification Engineer with a proven track record of developing and executing verification plans to ensure the functionality of complex digital designs. Proficient in developing testbench architectures and test cases, debugging failures using industry-standard verification tools and languages such as System Verilog, UVM. Successfully verified HMAC ASIC design in the role of DV engineer. Seeking a challenging role to contribute my expertise in verifying complex digital designs and enhancing the quality of the product.
Experience
Senior Silicon Engineer
Nov 2024 — Present · Bengaluru, IN
Education
Indian Institute of Technology Hyderabad
Master of Technology (M.Tech.), Microelectronics and VLSI
2014 — 2017
Gayatri Vidya Parishad College of Engineering (Autonomous)
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
2008 — 2012
Skills
- Pl/Sql
- Vhdl
- Simulations
- Linux
- Modelsim
- C
- Programming
- Engineering
- Unix
- Cadence Virtuoso
- Digital Circuit Design
- Microsoft Office
- Vlsi
- Matlab
- Field-Programmable Gate Arrays (Fpga)
- Analog Circuit Design
- Very-Large-Scale Integration (Vlsi)
- Signal Processing
- Verilog
- Pspice
- Microcontrollers
- Fpga
- Asic
- Microsoft Word
- Electronics
- Xilinx Ise
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.