Sabareesh Thangaraj
DDR Memory Controller Design Engineer at Microsoft || Experienced DV engineer || Folks, connect @topmate for 1-1 on career, upskilling discussion || TAs, please connect if you have any strong design requirements.
- Role
- Design Engineer at Microsoft
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sabareesh Thangaraj
connect 1-1 for career discussion: https://topmate.io/sabareesh_thangaraj/11 years of experience in functional verification of DRAM Memory controller, NVMe Host Controller and AMD server/client SOC datapath verification.Expertise in testbench architecture and component development in SV, UVM, Specmen. Protocol - NVMe, DDR4, DDR5 and NVDIMMISA - x86
Experience
Design Engineer
Oct 2023 — Present · Bengaluru, IN
Azure Server SoC development mission | Cobalt Gen2/3product10 years experienced DV engineer pursuing design and micro-architecture role!Contributing to memory controller IP design team. Proficient knowledge in memory controller and PHY architecture.
Education
Madras Institute of Technology (MIT) Campus
Bachelor of Engineering (B.E.), electronics and communication engineering
2009 — 2013
Skills
- Matlab
- System Verilog
- Verilog
- I Can Do My Best in the Field of Digital System Design and Hardware Implemention
- Xilinx Ise
- Microsoft Office
- Axi Protocol
- Uvm
- C
- Ddr3
- Digital Electronics
- Multisim
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