Prasanth Pedapalli

About Prasanth Pedapalli

Design Verification Engineer with 3+ years of experience in ASIC and SoC verification, focused on GPU execution units and coverage-driven sign-off, Currently at NXP Semiconductors, verifying GPU Shader Processor features using structured testplans, constrained-random testing, and assertions. Built UVM-based reusable testbenches, sequences, and coverage models achieving >95% functional coverage.Strong in SystemVerilog, UVM, SVA, and Formal Verification for protocol, temporal, and micro-architectural checks, Hands-on with RTL debug using Synopsys Verdi, waveform analysis, and assertion-based debugging, Experience optimizing regressions and simulation flows, improving debug turnaround and sign-off readiness, Previously worked on RTL design and verification of a next-gen 6G transceiver PHY at HCL Technologies.

Experience

1. Design Verification Engineer

   NXP Semiconductors

   Jun 2024 — Present · San Jose, CA, US

   Performed end-to-end verification of performance-critical execution unit features within the GPU Shader Processor(SP) block, driving sign-off readiness through structured testplans, coverage-driven methodologies, and closuremetrics. Developed UVM-based verification environments, including modular testbench components, BFMs, and reusablesequences; authored constrained-random and directed test scenarios, achieving More than 95% functionalcoverage across complex datapath and control logic features. Designed and integrated functional coverage models and SystemVerilog Assertions (SVAs) for temporal, protocol,and micro-architectural checks, ensuring exhaustive corner-case validation and robustness under concurrentworkloads. Streamlined debug using Synopsys Verdi with assertion-based debugging, waveform analytics, and hierarchicalsignal tracing, reducing debug turnaround by 30% and accelerating critical-path closure. Partnered cross-functionally with RTL, architecture, and performance modeling teams to resolve micro-architecturalhazards, pipeline stalls, and scheduling anomalies, aligning execution-unit behavior with GPU performance andreliability goals. Optimized regression infrastructure, improving simulation throughput, test reproducibility, and failure triageefficiency to accelerate coverage progression and sign-off reporting. Authored detailed verification documentation (methodology guides, coverage reports, debug guidelines) to supportknowledge transfer, audits, and reuse across GPU design cycles

Education

• Vel Tech Rangarajan Dr. Sagunthala R & D Institute of Science & Technology, Chennai

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

• Portland State University

  Master's degree, Electrical and Computer Engineering