Saahithi Y.
Ic Packaging Engineer @AMD
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WORK HISTORY
Ic Packaging Engineer @AMD
Toronto, ON, CA
EDUCATION
Jawaharlal Nehru Technological University
Bachelor's degree, Electrical and Electronics Engineering
University at Buffalo
Master's degree, Electrical and Electronics Engineering
SKILLS
ABOUT SAAHITHI Y.
Expertise in design of silicon and substrate layouts including UCIe, D2D high speed interface, TSV & RDL interposers, FOWLP packages for applications such as AI HPCs, Automobiles, Mobile phones etc. Prior experience in ASIC designs. Deep understanding of - Top-level Layout Architecture, Floorplan, Auto/AI-Assisted Placement & Routing, Timing, DRCs, LVS, EMIR, Parasitics and Reliability Analysis. Development of 2.xD/3DIC methodologies to automate & co-design Silicon & Substrate using 3dblox, enabling cross-platform functionality across various EDA vendors.
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