S V H Hemanth Brahmarapu

WORK HISTORY

ABOUT S V H HEMANTH BRAHMARAPU

Working as a Digital Design Intern at STMicroelectronics and Actively looking for a career opportunity in VLSI domain.Experienced in Physical design, Synthesis and PnR,RTL Design and Verification using verilog and system verilog.Performed RTL to GDSII flow for various designs like RAM, Shift Register, bch-Ip etc.Implemented TMR, ΔTMR and Multibit FF in a Radiation Hardened Design and written a paper on this Design flow.Performed RTL verification to various designs.Exposed to Static Timing Analysis,tcl,Perl.Experienced in Digital design simulations using eldo.Experienced in LEC and formal verifications for designs including Radiation Hardened designs.Achievements:Qualified GATE in three papers EE,EC,IN with ranks below