Ruthvin Suvarna

About Ruthvin Suvarna

SoC/RTL Design Engineer experienced in ASIC design,functional verification, Post…

Experience

1. Soc Design Engineer

   Intel

   Mar 2015 — Present

   OmniPath Architecture,200Gb/s (4x50Gbps SERDES link)port :\\\\n• RTL Design of FEC error injection mechanism for RS(528,512) and RS(132,128) FEC.\\\\n•.Functional Verification of FEC/CRC encoder/decoder blocks. Lowest Latency reset position\\\\ndetermined for TX and RX FIFO read pointers.\\\\nEthernet Port IP:\\\\n• Owned the 400Gbps TDM Transmit MAC logic block development.\\\\n• Developed FSM for Link Fault Signaling as per clause 81.3 in the Reconciliation Sublayer of\\\\nPHY.\\\\n• MAC Client Adapter, Medium Independent Interface (MII) and Virtual MII loopback modes and\\\\nCSR’s added (SystemRDL) to assist validation team in debugging and develop Verification\\\\nenvironment.\\\\n• Created 2 frame channels to handle frames for maximum bandwidth and merged their outputs.\\\\nPreamble, SFD, EOP, Frame check sequence (FCS) and Idle insertion performed.\\\\n• Clock Gating implemented to save power.\\\\nOmniPath Architecture Gen2 :\\\\n• Post-Si validation: Developed tests for Functional Validation of FEC RS(528,512) and RS(132,128))\\\\nand CRC (all 4 types) and FEC error injection. Successfully tested FEC, CRC operation and FEC error\\\\ninjection on the APR switch & its FPGA build.\\\\n• Developed scripts for Burst error testing using FEC to measure the burst error length. Tests written\\\\nto collect BER/SER /lane across a channel for all combinations of FEC & CRC.\\\\nOmniPath Architecture Gen1 :\\\\n• Test development and scripting for active optical cables (AOC), firmware bug fixes, voltage range\\\\ntests,etc.\\\\n \\\\n\\\\n \\\\n \\\\n\\\\n \\\\n

Skills

• Fpga
• Spw
• Modelsim
• Xilinx Ise
• Vlsi
• Synopsys Primetime
• Cadence Virtuoso
• Vhdl
• Static Timing Analysis
• Pspice
• Synopsys Icc
• Tcl
• Design for Testability (Dft)
• Synopsys Design Vision
• Digital Signal Processors
• Microsoft Office
• Matlab
• Verilog
• Perl
• C++
• Xilinx Vivado
• Asic
• C
• Python