About Rushit Shah
Versatile Engineer with 12+ years of experience in SOC/IP Functional Verification…
Experience
Present
Skills
- Modelsim
- Keil
- Microprocessors
- Hardware
- First Encounter
- Cadence Spectre
- Simulations
- Functional Verification
- Ovm
- Drc
- C++
- Ms Office Suite
- Vlsi
- Lvs
- Cadence
- Primetime
- Synopsis Design Compiler
- Rtl
- Static Timing Analysis
- Digital Electronics
- Cadence Virtuoso Layout Editor
- Systemverilog
- Windows
- Tcl
- Physical Design
- Synopsys Primetime
- Universal Verification Methodology (Uvm)
- Verilog
- Formal Verification
- Soc
- Clock Tree Synthesis
- Hardware Architecture
- Cadence Virtuoso
- Cacti
- Asic
- Cmos
- Application-Specific Integrated Circuits (Asic)
- Rtl Design
- Layout Versus Schematic (Lvs)
- Logic Synthesis
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