Rupesh Singh

About Rupesh Singh

Area of Interest: Physical design, STA, Full Chip related work, AVF, APFTool - ICC2, FC, INNOVUS, Genus, PRIME Time, Caliber Work Experience-* Worked on verious technology node with different Foundary. Latest working on 4LPP with samsung foundary in SSIR.* Working experience for Digital and Analog IP for PnR & Signoff execution.*Good understanding of Physical design flow & Signoff.*Hands on experience of backend flow such as Floor-Planning, Place and route,CTS, Block level Timing Enclosure, Static IR drop Analysis, Sanity checks, Noise analysis.*Familiar with verification methodologies like DRC, LVS, ERC.*Good understanding of Static Timing Analysis & ETM model generation.*Thorough knowledge of digital circuit design concepts.*Strong fundamental knowledge of semiconductor concepts.*Good knowledge of analog design concepts, and MOSFET.*Basic understanding of Perl & TCL.I have good understanding of Physical Design, Digital VLSI Design, VLSI Design Concepts and VHDL, Verilog Programming through various course works in my M.Tech courses. I have excellent interpersonal and communication skills.I would describe myself as a motivated, hard working and ambitious individual with an aptitude of always looking to learn new things

Experience

1. Senior Staff Engineer

   Samsung Semiconductor

   Mar 2025 — Present

Education

• S. M inter college, Hajipur

  Intermediate , Science

  2005 — 2007

• Visvesvaraya National Institute of Technology

  Master's degree, VLSI DESIGN

  2015 — 2017

• Lakshmi Narayan College of Technology, BHOPAL

  Bachelor's degree, Electronics and Communications Engineering

  2009 — 2013

• S.S.V.M.ramdauli

  matriculation , Mathematics

  2004 — 2005