Ruofei Yan
Graduate student @ UIUC｜Hardware Intern @ Apple, Arista Networks | EE 24\' @ NJU
- Role
- Hardware Design Engineer at Arista Networks
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Ruofei Yan
Hardware Engineering: System EE: Schematic Capture, PCB Layout, Signal/Power Integrity, Analog/High-Speed Design, EDA Tools (Cadence Allegro & Altium Designer), Simulation Tools (LTspice, Tina-TI, Multisim), Lab Tools: Oscilloscope, DMM, Spectrum Analyzer, Network Analyzer, Power MeterCMOS IC: Schematic Capture, IC Layout, EDA Tools(Cadence Virtuoso), Simulation Tools(HSPICE)- Coding: C, Python, C++, MCU Firmware Development, MATLAB- Languages: English (TOEFL 104), Mandarin (Native Speaker)
Experience
Hardware Design Engineer
May 2025 — Present · Santa Clara, CA, US
Education
Nanjing University
Electronic Information Science and Technology
2020 — 2024
University of Illinois Urbana Champaign
Masters Degree, Electrical and Computer Engineering
2024 — 2026
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