Rangarajan S.

About Rangarajan S.

Working for last 6+ years in Qualcomm, Chennai. Currently leading a SOC Physical design…

Experience

1. Distinguished Engineer

   NVIDIA

   Oct 2023 — Present · Chennai, IN

   Part of CPU Implementation team

Education

• Anna University

  Bachelor of Engineering

  1998 — 2002

• Indian Institute of Science

  M.Tech

  2003 — 2005

Skills

• Vhdl
• Soc
• Verilog
• Integrated Circuit Design
• Timing
• Perl
• Eda
• Physical Design
• Application-Specific Integrated Circuits (Asic)
• Vlsi Cad
• Primetime
• Tcl
• Static Timing Analysis
• System on a Chip (Soc)
• Dft
• Synthesis
• Floorplanning
• Vlsi
• Silicon
• Timing Closure
• Asic
• Computer Architecture
• Logic Synthesis