Karen Rowell

About Karen Rowell

Integration, physical design, floor planning, clock planning and insertion, routing, custom wiring, timing closure, and synthesis of server chips, ASICs, semi-custom chips, system on a chip, memory chips, and processor cores. Experience with low power implementation, power gating, multiple voltage rails, em and ir drop mitigation, and physical verification in advanced technology nodes.Innovating design practices, methodologies, and flows.Experience in EDA supporting full RTL->GDS2 flows and hands on Physical Design.

Experience

1. Principal Physical Design Engineer

   Marvell Technology

   Mar 2019 — Present · Morrisville, NC, US

   Physical Design Engineer with extensive knowledge of the ASIC/SOC flow from Synthesis to GDSII. Experience with emerging technologies and solutions in the electronic design automation industry. Synthesis, Place and route, clock insertion, optimization, timing closure, noise reduction, metal only ecos, drc, and lvs of complex 7nm, 5nm, and 3nm intergrated circuits.

Education

• University of North Carolina at Charlotte

  BSEE, Electrical and Electronics Engineering

Skills

• Debugging
• Systemverilog
• Floorplanning
• Hardware
• Rtl Design
• Functional Verification
• Soc
• Vhdl
• Simulations
• Spice
• Timing
• Logic Design
• Signal Integrity
• Low-Power Design
• Arm
• Logic Synthesis
• Electrical Engineering
• Drc
• Lvs
• Cadence Virtuoso
• Ic
• Perl
• Embedded Systems
• Eda
• Static Timing Analysis
• Integration
• Timing Closure
• Processors
• Clock Tree Synthesis
• Mixed Signal
• Circuit Design
• Cmos
• Semiconductors
• Hardware Design
• Integrated Circuit Design
• Microprocessors
• Computer Architecture
• Vlsi
• Modelsim
• Place & Route