Ron Kimmel
Retired- Now playing softball 4 days a week and flipping houses at Self-Employed
- Role
- New Technology Development Manager at Intersil Acquired By Renesas
- Location
- Fremont, CA, US
- LinkedIn followers
- 500 followers
About Ron Kimmel
Summary:Engineering Test Manager our group develops test hardware / software to meet new product release dates. Expert at solving mechanical issues when mating handlers, and probers to test systems. Designs test interface boards for the Eagle 364 and the Teradyne Flex test Systems.Manages Probe Card / Test Hardware Assemble groups. Evaluates different probe card styles; Cantilever, Buckling Beam, pogo, membrane and Silmat. Designs docking for prober setups. Major contributor with integrating CSP, Film Frame and Strip Test setups. Expertise includes:• Mechanical ability (design and FAB)• Developing new manufacturing methods• Integrating new test equipment and processes• Inventing cost saving processes and systems • Test methodology (Including environmental chambers, and shock and vibration equipment)• Troubleshooting• Verbal and written communication skills. • Analytical and critical thinking skills.• Ability to specify complex test environmental fabrication • Managed/designed development of electrical and mechanical systems.
Experience
New Technology Development Manager
Jan 2009 — Present · Milpitas, CA, US
1001 Murphy Ranch RD. Milpitas, CA. April 2009 to present: Position: TEST TECHNOLOGY DEVELOPMENT ENGINEERING MANAGER• US Patent # US 8,203,354 B2 inventor. This patent reduces hardware cost because only one test board is needed to test all product packages. It also doubled the test circuit layout area.• equipment/production cost savings; invented test modules that were added to the tester that doubled the number of devices that could be tested in parallel.• cost saving by designing and building a light source module for testing Intersil’s Light/Proximity Sensor products. Did all the mechanical design to add different wave length light sources to Intersil’s light source modules.• cost saving per wafer probe setup from my low cost wafer sort tower design. Plus the added advantage the test circuit layout area was quadruped.• 48 sq. in. added to the probe card layout area close to the devices being probed by a Probe Tower modification. This doubled the through put by enabling more parallel test sites.
Skills
- Power Management
- Spc
- Pcb Design
- Integrated Circuit Design
- Cmos
- Semiconductors
- Sensors
- Test Engineering
- Product Engineering
- Hardware Architecture
- Debugging
- Analog
- Analog Circuit Design
- Fpga
- Bist
- Mixed Signal
- Circuit Design
- Ic
- Rf
- Testing
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