Romany Grais
Staff Implementation Engineer @Arm
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WORK HISTORY
Staff Implementation Engineer @Arm
Cambridge, GB
Clock Domain Crossing (CDC) timing constraints development in large number of blocks and higher complexity of domain crossings
EDUCATION
Cairo University
Master of Science (M.Sc.), Electronics Engineering
Cairo University
Bachelor of Science (B.Sc.), Electronics and Communications Engineering
SKILLS
ABOUT ROMANY GRAIS
Specialties: All aspects of physical design from RTL to GDSII- Unified Power Format (UPF)- Logic Synthesis- DFT Insertion- Formal Verification- Floorplan (Flat and Hierarchical)- Integration of macros, memories/analog IPs- Power Grid design- Power analysis (Static IR drop, Dynamic IR drop, Signal Integrity, Electromigration)- RDL Routing (Die Driven and Package Driven)- Placement, CTS and Routing- STA, timing closure and signoff- Physical Verification (DRC, LVS, DFM), physical closure and signoff- Design and flow automation- Makefile- UNIX and CSH- TCL scripting- Perl scriptingSiemens Tools- QuestaCDC- QuestaSim- PowerPro - CalibreANSYS Tools- RedHawkCadence EDA Tools- Genus - Conformal LEC - Conformal Low Power (CLP)- Innovus - Quantus QRC - TempusSynopsys EDA Tools- Fusion Compiler - Design Compiler - Formality - IC Compiler - Primetime - PrimeRail - Star-RCXT - Hercules - IC Validator - IC Workbench - Milkyway
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