Romana Fernandes
Hardware Engineering Manager
- Role
- Hardware Engineering Manager at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Romana Fernandes
Under graduation in Electronics and Communications at PESIT, India. Design Engineer at Agere Systems, India. Work experience involved Physical Design Kit Validation. Senior Design Engineer at LSI, India in standard cell development. Masters in VLSI Systems at the University of Cincinnati, USA.Intern at Apache design, worked on power analysis tool / flow.Currently working at Nvidia. Experience includes automatic placement and routing, timing closure and power analysis.Specialties: Physical Design Kit verification and development.Standard Cell Library Development.Automatic place and route, timing closure and power analysis.Adept in the usage of Industry standard EDA tools like Cadence Composer, VirtuosoXL, Spectre, Ultrasim, Assura, Cadence Open Access, Hercules, StarRCXt, Cadabra, Hspice Calibre, Talus, ICC, Pinnacle, Prime time, Red hawk, EPS.
Experience
Hardware Engineering Manager
Jun 2022 — Present · San Francisco, CA, US
Education
Visvesvaraya Technological University
Bachelors in Engineering, Electronics and Communication
2000 — 2004
University of Cincinnati
MS, VLSI Systems
2007 — 2009
Mount Carmel College
XII, Physics, Chemistry, Math, Biology
1998 — 2000
Stanford University
Management Science and Engineering Graduate Certificate
2012 — 2015
Skills
- Vlsi
- Power Analysis
- Spectre
- Spice
- Timing Closure
- Physical Design
- Drc
- Primetime
- Place & Route
- Cmos
- Lvs
- Cadence
- Verilog
- Hercules
- Perl
- Eda
- Static Timing Analysis
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