Rohith T.
.
- Role
- Validation Engineer at Intel
- Location
- Sacramento, CA, US
- LinkedIn followers
- 500 followers
About Rohith T.
Experienced and detail-oriented Post-Silicon Validation Engineer with a strong background in validating complex SoCs and hardware systems. Proficient in creating and executing validation test plans, debugging hardware/software issues, and collaborating with cross-functional teams to ensure first-silicon success. While I’ve built a solid foundation in post-silicon validation, I’m also eager to broaden my expertise and explore adjacent fields and I’m looking for opportunities where I can leverage my hardware background while learning and contributing to new technical areas.
Experience
Validation Engineer
Jul 2021 — Present
Intel Custom Accelerator MGR- Proficient in RAS (Reliability, Availability, Serviceability) and Power Management flows, with strong experience in content development and automation using PythonSV and Shell scripting- Skilled in using the NGA (Next Generation Automation) tool for automating test execution and validation processes- Strong debug expertise across RAS, PM, MSG (Memory Stress Generation), and RIG (Random Instruction Generation), with a proven ability to identify root causes and deliver effective solutions- Experienced with the MOKA OS validation tool, including XML modifications for register-level checks, and hands-on with the MARS validation framework for test setup and execution- Familiar with filing sightings, pre-sightings, and lab tickets, actively involved in system-level debug and validation report communication- Proficient in Git version control for managing and updating automation scripts and creating YUM packages for software deployment- Solid understanding of MGR SoC architecture, with a strong focus on test development, environment setup, and detailed validation documentation.Intel Xeon Server SOC DMR- Understand the test plan for scalable coherent fabric, port multiple scripts from previous projects to current project- Setting up for DMR boundary scan, creating a test plan, setting up equipment and readiness.
Education
GOWTAHM MODEL SCHOOL
SSC
2008 — 2010
Jb Institute Of Engineering and Technology
Bachelor's Degree, Electrical, Electronics and Communications Engineering
California State University-Sacramento
Master's Degree, Electrical and Electronics Engineering
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