Rohith Raj

Analog Layout Engineer @Apple

Munich, DE

EMAILS

[email protected]

MOBILE NUMBERS

+91 *********19

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WORK HISTORY

May 2024 — Present

Analog Layout Engineer @Apple

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Munich, DE

EDUCATION

2012 — 2014

K.C.G College of Technology Chennai

Master of Technology (M.Tech.), VLSI Design

2007 — 2011

Government Engineering College Idukki

Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

SKILLS

Digital ElectronicsVlsiLayoutCmosAsicCadence Schematic CaptureCadence VirtuosoStatic Timing AnalysisCadence Virtuoso Layout EditorTanner EdaSramSynopsys Custom DesignerMemory LayoutSemiconductor FabricationEdaVery-Large-Scale Integration (Vlsi)SemiconductorsDebuggingApplication-Specific Integrated Circuits (Asic)

ABOUT ROHITH RAJ

IC Layout professional with 8+ years of experience in Analog Layout design and Verification using Cadence Virtuoso. Currently working at Renesas Design GmbH Germany as Senior Analog Layout Engineer in PMIC Team. Technological exposure in GF55BCD, TSMC90BCD, TSMC130BCD, Intel 10nm, Intel 14nm, TI-LBC9, TI-LBC8LV processes. Successfully taped-out 2 chips as a full-chip layout lead & managed a team size of 20 plus engineers from multiple sites.

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