Rohith Gm

About Rohith Gm

Functional RTL Verification- Exceptional OOP (SystemVerilog) and scripting skills (Perl, Python, etc.)- Experience with constraint programming (SystemVerilog) and structured hardware verification methodology (UVM)- Working Knowledge of ONFI,DDR3, DDR4, DFI3.1, AXI, DDR PHY- UWB based sub-system and SoC level verification- RF based wireless charging receiver SoC verification- Development of UVM RAL from scratch- Worked on developing UVCs, testplan, testcases, sequences,running regressions, RTL debug, assertions, functional coverage- AMS verification of IO, MDLL, SDLL, PLL and DDR PHY(Spice vs Verilog consistency - LEC)- SDF back annotation, GLS simulations- Verilog modelling of analog components (gate and behavioral modelling)

Experience

1. Principal Engineer

   Micron Technology

   Nov 2024 — Present

Education

• PES Institute of Technology

  Master of Technology (M.Tech.), VLSI design and Embedded systems

  2012 — 2014

• Visvesvaraya Technological University

  Bachelor of Engineering (BE), Electronics and Communications Engineering

  2006 — 2010

Skills

• Debugging
• Systemverilog
• C
• Sql
• Soc
• Vlsi
• Fpga
• Simics
• Cadence
• Verilog
• Rtl Coding
• Wireshark
• Simulations
• Rtos
• Soc Emulation
• Embedded Systems
• Cadence Virtuoso
• Xilinx Ise
• Python
• Shell Scripting
• C++
• Functional Verification
• System Verilog
• Cmos