Rohit Singh
CPU Power Management Pre-Si Validation Engineer at Intel | Former 2021 Grad - MS in Computer Engineering at USC | End-End full-chip debug | UVM | Computer \"Low Power\" Architecture
- Role
- Cpu Power Management Validation Engineer at Intel
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Rohit Singh
A cross-disciplinary thinker with an interest in Hardware engineering. Skilled in Digital System Design, Computer Architecture, Python, Verilog, System Verilog, and C++.(Exposure to high-performance Computing CUDA programming), PCIe Gen 3, AMBA Architecture, ARM\'s AXI Protocol, Multi-Chip CPU Processor Architecture. Performed Directed Research under Dr. Alice Parker. A Fall 2021 Graduate pursuing a Masters in Computer Engineering at the University of Southern California Viterbi School of Engineering. At Accenture,gained experience with IT Services and served clients in Food and Agri-Cargill, Automotive- Volkswagen, and Medicare- Phyzer. Have experience working within large teams of engineers. Excellent communication skills: verbal, written, presentations, executive interaction, leading meetings. Strong communication skills, team player working in a collaborative work environment, discipline and planning; Experience in problem-solving, including root cause analysis and DOE creation. Ability to break down complex problems into actionable parts. At Intel, worked at E-Core SOC Design Team, for verifying specific IP’s feature for client and server, focusing on clocking and reset/power verification.Looking for an Full-time ASIC, SOC Design and verification engineer/Digital VLSI/RTL Design jobs.
Experience
Cpu Power Management Validation Engineer
Jun 2021 — Present · Austin, TX, US
Involved in end-to-end Pre Silicon Reset Flow and Power validation scope for Intel’s Low Power/Perf CPU IP. Written Validation Test Plan, System Verilog Assertions, Checkers, and Coverages for Intel\'s new-gen IC. Supporting DCAI’s group new-gen Efficiency cores. Feature Validation owned : DiDT power saving, Telemetry CLOS ASOS data, Full Chip : ASM test simulator.
Education
Loyola School Jamshedpur
ICSE, Indian/Native American Education
2000 — 2012
Vellore Institute of Technology
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2012 — 2016
University of Southern California
Master's degree, Computer Engineering, Spec. In VLSI Design and architecture
2019 — 2021
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