Rohit Singh
Design and verification engineer || VLSI || RTL Design || Verification || 3ST Technologies Pvt Ltd Rustam ji institute of technology Border Security Force (BSF) Tekanpur Gwalior 474005
- Role
- Design and Verification Trainee at 3st Technologies
- Location
- New Delhi, DL, IN
- LinkedIn followers
- 500 followers
About Rohit Singh
Trained Design and verification engineer Knowledge of Digital electronics, Verilog, STA, CDC, System verilog - Assertions,Coverage, Randomization, UVM Methodology, C with DSA, C++ with OOPS Concepts, Linux, Perl Scripting->>Also worked on Projects Like - Designed these projects using \"Verilog\"> AMBA (APB PROTOCOL)> FIFO Buffer > UART Protocol > I2C ProtocolVerification of below projects using \"System verilog\"> APB PROTOCOL > Synchronous FIFO > Full Adder > 4bit Counter > D Flip Flop
Experience
Design and Verification Trainee
Sep 2023 — Present
Education
Rustamji Institute of Technology, Border Security Force (BSF) Academy, Tekanpur, Gwalior 474005
Bachelor of Technology - BTech
2020 — 2023
BSF POLYTECHNIC STS TIGRI DELHI
Diploma
2017 — 2020
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