Rohit Shandilya
- Role
- Senior Design Verification Engineer at 高通
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
Experience
Senior Design Verification Engineer
Nov 2020 — Present
Skills
- Logic Design
- Pspice
- Proteus
- Teamwork
- Application-Specific Integrated Circuits (Asic)
- Simulations
- Vlsi Cad
- Programming
- Semiconductors
- Java
- Microsoft Word
- Powerpoint
- Cadence
- Microsoft Office
- Matlab
- Static Timing Analysis
- Cadence Virtuoso
- Eagle Pcb
- C
- Computer Architecture
- Cadence Spectre
- Microsoft Excel
- Research
- Electronics
- Debugging
- Very-Large-Scale Integration (Vlsi)
- Microsoft Powerpoint
- Digital Ic Design
- Python
- C++
- Digital Circuit Design
- Validation
- Verilog
- Functional Verification
- Eda
- Microcontrollers
- Cmos
- Altera Quartus
- Systemverilog
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