Rohit S.
Lead Design Engineer-Analog Design @ Cadence
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rohit S.
Completed Master of Technology in Microelectronics and VLSI from NIT Durgapur Currently working as Analog Design Engineer and worked on various process nodes such as samsung 4nm, intel 7nm, tsmc28nm, gf40nm, 65nm Experience of working on protocol like Memory interface Gen6p9 DDR5/LPDDR5 PHY (cmd TX, ClkLogic, clock buffer block) and PCIe Gen 3/4 (8Gbps, 10Gbps SERDES TX) Familiar with OP Amp, BGR, LDO, Serializer, Driver, Resistance Termination, Receiver Detect, and ESD blocks in high speed SERDES Worked on Reliability analysis such as Aging, RV (EMIR), EOS, and ERC, Monte Carlo simulations Ability to analyze Electrical Specifications and create Test Benches to meet functionality. Well known with DC analysis, Transient analysis, AC analysis, Stability analysis, PSRR Simulations. Published M.Tech. Project research paper in 26th International Conference on Very Large Scale Integration (VLSI-SoC) held in Verona, Italy
Experience
Lead Design Engineer
Sep 2024 — Present · Hyderabad, IN
Education
Kavi Kulguru Institute of Technology and Science, Ramtek
Bachelor of Engineering (B.E.) , Electronics and Communications Engineering
2011 — 2015
National Institute of Technology Durgapur
Master of Technology (MTech), Microelectronic and VLSI
2016 — 2018
Skills
- Research
- Microsoft Excel
- Powerpoint
- English
- C++
- Social Media
- Java
- Teamwork
- Public Speaking
- Photoshop
- Customer Service
- Html
- C
- Microsoft Office
- Microsoft Word
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